Semiconductor device and its manufacturing method

ABSTRACT

A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film comprising a first insulating film and a second insulating film formed on the first insulating film, the first insulating film comprising a silicon oxide film containing carbon of a concentration, the second insulating film comprising a silicon oxide film containing carbon of a concentration lower than the concentration of the first insulating film or comprising a silicon oxide film containing substantially no carbon, a via contact made of a metal material embedded in a via hole formed in the interlayer insulating film, a diameter of the via hole in the first insulating film being smaller than that in the second insulating film at an interface between the first insulating film and the second insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2003-003290, filed Jan.9, 2003, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and amethod of manufacturing the same, and more particularly to a sectionalshape of metal wiring or via contact in multilayer wiring using aninterlayer insulating film containing carbon and a method of forming thesame, being used, for example, in a semiconductor integrated circuithaving metal wiring or via contact using copper (Cu) or Cu alloy.

[0004] 2. Description of the Related Art

[0005] Recently, in the trend of higher speed of LSI, a film of lowdielectric constant comes to be used as interlayer dielectric (ILD) ofmultilayer wiring. The relative dielectric constant of a conventionalSiO₂ film is about 4.0, the relative dielectric constant of a SiO₂ filmcontaining fluorine is about 3.4 to 3.9, and an insulating film of lowerrelative dielectric constant of 3 or less is also recently used.

[0006] Generally, however, materials of low dielectric constant are weakin mechanical strength. Besides, carbon is often contained in the filmin order to lower the dielectric constant. In such a case, the addedcarbon or CH₃ (methyl group) may be damaged to lower the carbonconcentration by a dry process such as resist ashing or reactive ionetching (RIE).

[0007] To prevent mechanical damage by chemical mechanical polishing(CMP) or damage by dry process, it has been attempted to form aninterlayer insulating film by laminating insulating films of differentcarbon concentrations. The interlayer insulating film of this structureis effective against mechanical or chemical damage from above the film,however, the side surface of the wiring groove or via hole is lower ineffectiveness because the film of low dielectric constant is exposed.

[0008] Problems of the interlayer insulating film of this structure aresummarized below.

[0009]FIGS. 10A and 10B are sectional views of a semiconductor device insteps of a conventional method of manufacturing a semiconductor device,particularly showing the section of the semiconductor device in steps offorming via holes (or wiring grooves) in a multilayer wiring section.

[0010] As shown in FIG. 10A, a lower layer wiring 102 is buried in aninsulating film 101 on a semiconductor substrate 100, and an interlayerinsulating film 103 is deposited on the lower layer wiring 102 andinsulating film 101. The interlayer insulating film 103 has a laminatedstructure composed of a first insulating film 104 formed of a siliconoxide film (hereinafter, referred to as Si oxide film) containingcarbon, such as methyl siloxane, SiOCH, or SiOC, and a second insulatingfilm (for example, SiO₂, or SiOCH, low in carbon concentration) 105 oflow carbon concentration as a cap film laminated on the first insulatingfilm 104.

[0011] When via holes (or wiring grooves) 107 are formed in theinterlayer insulating film 103 of such structure, on the side surface ofthe first insulating film 104 defining the via holes, the concentrationof the contained carbon is lowered, and a damaged layer 106 of loweredcarbon concentration is formed in the manufacturing process such as RIEor resist ashing (peeling off).

[0012] Since the damaged layer 106 has a property close to that of SiO₂,in a wet etching process, which is described later, using chemicalsolution such as HF or NHF₃, it is likely to be dissolved and lost asshown in FIG. 10B, or contracted in a subsequent heating process. As aresult, the opening size of the via holes in the second insulating film105 is smaller than that in the first insulating film 104, andprotruding marks of opening edges of the second insulating film 105 areleft over in the openings of the first insulating film 104.

[0013]FIGS. 11A and 11B are sectional views of a semiconductor device insteps of another conventional method of manufacturing the semiconductordevice, particularly showing the section of the semiconductor device insteps of forming via holes (or wiring grooves) in a multilayer wiringsection.

[0014] As shown in FIG. 11A, the second insulating film 105 is formed bya plasma process on the first insulating film 104 functioning as a capfilm. In this case, a damaged layer 106 is formed on the top of thefirst insulating film 104. When a via hole (or wiring groove) 107 isformed in the interlayer insulating film 103, the damaged layer 106 isformed on the side surface of the first insulating film 104.for definingthe via holes in the manufacturing process such as RIE or resist ashing.The damaged layer 106 are also likely to be dissolved and lost in a wetetching process, which is performed later, using chemical solution suchas HF or NHF₃ as shown in FIG. 11B. As a result, as in theafore-mentioned example, protruding marks of opening edges of the secondinsulating film 105 are left over in the openings of the firstinsulating film 104.

[0015] The protruding marks of opening edges of the second insulatingfilm 105 left over in the openings of the first insulating film 104 asshown in FIG. 10B and FIG. 11B may cause to form thin portions ordisconnections in a barrier metal film formed when a wiring or via isformed in a subsequent step or an insufficient embedding of metal wiringmaterial (Cu or Cu alloy). These are not preferable from the viewpointof reliability of wiring. Also, at the time of heat treatment, the metalwiring may break out from the thin portion of the barrier metal film,which may lower the electromigration resistance or stress migrationresistance of buried wiring or via portions.

[0016] It has been attempted to decrease such protruding marks as muchas possible to optimizing the etching process, ashing process, cleaningprocess, and the like, however, ultimately protrusions are formed moreor less. Such phenomenon of protrusion is disclosed by K. Higashi et al.in “A Manufacturable Copper/Low-k SiO/SiCN Process Technology for 90nm-node High Performance eDRAM,” 2002 proceedings of IEEE IITC, pp.15-17.

[0017] As mentioned above, in the conventional multilayer wiringstructure of the semiconductor device, when the buried wiring or viacontact is formed in the wiring grooves or via holes formed in theinterlayer insulating film having a first insulating film composed of aSi oxide film containing carbon and a second insulating film of lowercarbon concentration (containing no carbon) formed on the firstinsulating film, thin portions or disconnections are formed in thebarrier metal, or the metal wiring material may be insufficientlyembedded.

BRIEF SUMMARY OF THE INVENTION

[0018] According to an aspect of the present invention, there isprovided a semiconductor device comprising: a semiconductor substrate;an interlayer insulating film formed on the semiconductor substrate, theinterlayer insulating film comprising a first insulating film and asecond insulating film formed on the first insulating film, the firstinsulating film comprising a silicon oxide film containing carbon of aconcentration, the second insulating film comprising a silicon oxidefilm containing carbon of a concentration lower than the concentrationof the first insulating film or comprising a silicon oxide filmcontaining substantially no carbon, a via contact made of a metalmaterial embedded in a via hole formed in the interlayer insulatingfilm, a diameter of the via hole in the first insulating film beingsmaller than that in the second insulating film at an interface betweenthe first insulating film and the second insulating film.

[0019] According to another aspect of the present invention, there isprovided a semiconductor device comprising: a semiconductor substrate;an interlayer insulating film formed on the semiconductor substrate, theinterlayer insulating film comprising a first insulating film and asecond insulating film formed on the first insulating film, the firstinsulating film comprising a silicon oxide film containing carbon of aconcentration, the second insulating film comprising a silicon oxidefilm containing carbon of a concentration lower than the concentrationof the first insulating film or comprising a silicon oxide filmcontaining substantially no carbon, a metal wiring of a metal materialembedded in a wiring groove formed in the interlayer insulating film, adiameter of the wiring groove in the first insulating film being smallerthan that in the second insulating film at an interface between thefirst insulating film and the second insulating film.

[0020] According to a further aspect of the present invention, there isprovided a method of manufacturing a semiconductor device comprising:forming an interlayer insulating film on a semiconductor substrate, theinterlayer insulating film comprising a first insulating film and asecond insulating film formed on the first insulating film, the firstinsulating film comprising a silicon oxide film containing carbon of aconcentration, the second insulating film comprising a silicon oxidefilm containing carbon of a concentration lower than the concentrationof the first insulating film or comprising a silicon oxide filmcontaining substantially no carbon, forming a via hole in the interlayerinsulating film, removing a damaged layer formed on a side surface ofthe first insulating film which defines a portion of the via hole, thedamaged layer being formed when the via hole is formed, and retreating aside surface of the second insulating film which defines a portion ofthe via hole, and embedding a metal material in the via hole to form avia contact in the via hole.

[0021] According to a further aspect of the present invention, there isprovided a method of manufacturing a semiconductor device comprising:forming an interlayer insulating film on a semiconductor substrate, theinterlayer insulating film comprising a first insulating film and asecond insulating film formed on the first insulating film, the firstinsulating film comprising a silicon oxide film containing carbon of aconcentration, the second insulating film comprising a silicon oxidefilm containing carbon of a concentration lower than the concentrationof the first insulating film or comprising a silicon oxide filmcontaining substantially no carbon, forming a wiring groove in theinterlayer insulating film, removing a damaged layer formed on a sidesurface of the first insulating film which defines a portion of thewiring groove, the damaged layer being formed when the wiring groove isformed, and retreating a side surface of the second insulating filmwhich defines a portion of the wiring groove, and embedding a metalmaterial in the via hole to form a metal wiring in the wiring groove.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0022]FIG. 1A is a sectional view of a semiconductor device in one stepof a method of manufacturing a semiconductor device according to a firstembodiment of the invention, particularly in a step of forming via holes(or wiring grooves) in a multilayer wiring section.

[0023]FIG. 1B is a sectional view of a semiconductor device in a furtherstep of the method of manufacturing the semiconductor device accordingto the first embodiment of the invention.

[0024]FIG. 1C is a sectional view of a semiconductor device in a furtherstep of the method of manufacturing the semiconductor device accordingto the first embodiment of the invention.

[0025]FIG. 2 is a characteristic diagram showing measurement data ofetching speed of a damaged layer, a first insulating film, and a secondinsulating film in HF solution in the wet etching process shown in FIG.1.

[0026]FIG. 3 is a sectional view showing modified example 1 of thesemiconductor device shown in FIG. 1C.

[0027]FIG. 4 is a sectional view showing modified example 2 of thesemiconductor device shown in FIG. 1C.

[0028]FIG. 5 is a sectional view showing modified example 3 of thesemiconductor device shown in FIG. 1C.

[0029]FIG. 6 is a sectional view showing modified example 4 of thesemiconductor device shown in FIG. 1C.

[0030]FIG. 7 is a sectional view of a semiconductor device in one stepof a method of manufacturing a semiconductor device according to asecond embodiment of the invention, particularly in a step of formingvia holes (or wiring grooves) in a multilayer wiring section.

[0031]FIG. 8 is a sectional view showing the structure of FIG. 7 in anarray state, for explaining the condition of retreat amount B of asecond insulating film 75.

[0032]FIG. 9 is a sectional view showing modified example 1 of thesemiconductor device shown in FIG. 7.

[0033]FIG. 10A is a sectional view of a semiconductor device in one stepof a conventional method of manufacturing a semiconductor device,particularly in a step of forming via holes (or wiring grooves) in amultilayer wiring section.

[0034]FIG. 10B is a sectional view of a semiconductor device in afurther step of the conventional method of manufacturing thesemiconductor device, particularly in a step of forming via holes (orwiring grooves) in a multilayer wiring section.

[0035]FIG. 11A is a sectional view of a semiconductor device in one stepof another conventional method of manufacturing a semiconductor device,particularly in a step of forming via holes (or wiring grooves) in amultilayer wiring section.

[0036]FIG. 11B is a sectional view of a semiconductor device in afurther step of the conventional method of manufacturing thesemiconductor device, particularly in a step of forming via holes (orwiring grooves) in a multilayer wiring section.

DETAILED DESCRIPTION OF THE INVENTION

[0037] Embodiments of the invention are described specifically belowreferring to the accompanying drawings.

FIRST EMBODIMENT

[0038]FIGS. 1A to 1C are sectional views of a semiconductor device insteps of a method of manufacturing a semiconductor device according to afirst embodiment of the invention, particularly in a step of forming viaholes (or wiring grooves) in a multilayer wiring section.

[0039] As shown in FIG. 1A, a metal wiring (lower layer wiring) 12 isburied in a first interlayer insulating film 11 formed on asemiconductor substrate 10, and a second interlayer insulating film 13is formed on the lower layer wiring 12 and first interlayer insulatingfilm 11. The second interlayer insulating film 13 has a laminatedstructure composed of a first insulating film 14 and a second insulatingfilm 15. The first insulating film 14 is formed on the lower layerwiring 12 and first interlayer insulating film 11, and the secondinsulating film 15 is laminated on the first insulating film 14.

[0040] The first insulating film 14 is formed of a silicon oxide film(hereinafter, referred to as SiO₂ film) containing carbon. The secondinsulating film 15 is of a low carbon concentration (or no carbon) andfunctions as a cap film. The first insulating film 14 is formed of suchas methyl siloxane, SiOCH, or SiOC, and the second insulating film 15 isformed of, for example, SiO₂, or SiOCH which is low in carbonconcentration.

[0041] Subsequently, a resist pattern (not shown) is formed on thesecond insulating film 15 by means of lithography, and a via hole 17 isformed in the second interlayer insulating film 13, as shown in FIG. 1A,by performing an RIE process, using the resist pattern as an etchingmask. Then, the resist pattern is removed by ashing.

[0042] Due to the RIE process and ashing process being performed, theconcentration of the contained carbon is lowered in the side surface ofthe first insulating film 14 defining the via holes, and a damaged layer106 of a lowered carbon concentration is formed.

[0043] A surface layer of a via hole side surface of the firstinsulating film 14 and a surface layer of a via hole side surface of thesecond insulating film 15 are dissolved by wet etching using a chemicalsolution containing HF, NHF₃ or the like, and removed as shown in FIG.1B. At this time, when the wet etching process is conducted for apredetermined period of time or more, the opening diameter in the secondinsulating film 15 is larger than that in the first insulating film 14at an interface between the first insulating film 14 and the secondinsulating film, 15 as shown in FIG. 1C.

[0044] The relation of the opening diameter between the first insulatingfilm 14 and the second insulating film 15 at the interface therebetweenis explained by referring to an example in which a process of definingthe relation of the opening diameter in the first insulating film<theopening diameter in the second insulating film is performed.

[0045] Since the damaged layer 16 formed at the side surface of the viahole 17 in the first insulating film 14 is lower in the carbonconcentration, and it is a film damaged by oxidation, it is dissolved inacid such as HF or NHF₃ and removed at the time of wet etching. Theetching rate of the damaged film 16 at this time is greater than that ofthe second insulating film 15, and the shape of the via hole 17 becomesas shown in FIG. 1B.

[0046] Since the damaged layer 16 is removed, the side surface of thefirst insulating film 14 is exposed to the side surface of the via hole.Since this exposed side surface is substantially free from effects ofRIE or resist ashing process in the forming process of the damaged layer16, its carbon concentration is maintained nearly in the state beforethe process. Accordingly, the first insulating film 14 exposed to thevia hole side surface is extremely low in the etching rate by HF, NHF₃or the like. On the other hand, the second insulating film 15 ofrelatively low carbon concentration is intermediate in the etching rateby FN, NHF3 or the like between the damaged layer 16 and firstinsulating layer 14.

[0047] Therefore, after the damaged layer 16 is dissolved, the secondinsulating film 15 is etched faster than the first insulating layer 14.By properly selecting this etching time, as shown in FIG. 1C, therelation of the opening diameter between the first insulating film 14and the second insulating film 15 at the interface therebetween may bedefined in the relation of the opening diameter in the first insulatingfilm<the opening diameter in the second insulating film.

[0048] That is, since the opening edge of the second insulating film 15retreats from the axis of the via hole 17 more than the opening edge ofthe first insulating layer 14, then disconnections of the barrier metallayer 18 can be prevented in a subsequent step of forming a barriermetal film 18. Also, in a subsequent step of forming a via contact 19 byburying a metal material (Cu or Cu alloy) in the via hole 17,insufficient embedding of the metal material (Cu or Cu alloy) in the viahole is prevented, so that the reliability of the wiring is enhanced.

[0049]FIG. 2 is a characteristic diagram based on measurement data ofetching rate of the damaged layer 16, second insulating film 15, andfirst insulating film 14 in, for example, HF solution in the wet etchingprocess executed in the step shown in FIGS. 1B and 1C. Herein, the HFsolution contains H₂O and HF at a ratio of, for example, 100: 1 by vol.%. On the basis of this characteristic diagram, the retreat amount B ofthe second insulating film 15 at the interface between the firstinsulating film 14 and the second insulating film 15 may be determined.

MODIFIED EXAMPLES OF FIRST EMBODIMENT

[0050] Modified examples of sectional shapes of via holes (or wiringgrooves) are described hereinafter, in which the relation between theopening diameter in the first insulating film 14 and the openingdiameter in the second insulating film 15 at the interface therebetweenis defined to be a relation of the opening diameter in the firstinsulating film<the opening diameter in the second insulating film, asdescribed in the first embodiment.

[0051]FIG. 3 is a sectional view of a multilayer wiring structureaccording to modified example 1 of the first embodiment.

[0052] A via hole (or wiring groove) 171 shown in FIG. 3 is differentfrom that shown in FIG. 1C in that the side surface of the secondinsulating film 15 for defining the via hole is tapered. That is, theside surface of the second insulating film 15 for defining the via holeis tapered in a manner that the opening diameter in the secondinsulating film 15 is greater as the position on the opening is moreaway from the interface between the first insulating film 14 and thesecond insulating film 15. Other parts or portions are the same as thoseused in FIG. 1C, and thus identified with same reference numerals asthose used in FIG. 1C.

[0053] The second insulating film 15 is processed in various shapesdepending on the processing conditions. In the structure in FIG. 3, therelation of the opening diameter at the interface between the firstinsulating film 14 and the second insulating film 15 is defined suchthat the opening diameter in the first insulating film<the openingdiameter in the second insulating film is obtained. Therefore, the sameeffects as in the first embodiment are obtained.

[0054]FIG. 4 is a sectional view showing a part of a multilayer wiringstructure according to modified example 2 of the first embodiment.

[0055] A via hole (or wiring groove) 172 in FIG. 4 is different fromthat shown in FIG. 3 in that the opening edge section of the firstinsulating film 14 (the shoulder of the opening edge of the firstinsulating film 14) is tapered. That is, the opening edge section of thefirst insulating film 14 (the shoulder of the opening edge of the firstinsulating film 14) is tapered by RIE or the like such that the openingdiameter of the opening edge section of the first insulating film 14 isgreater as the position on the opening is closer to the interfacebetween the first insulating film 14 and the second insulating film 15.Other parts or portions are the same as those used in FIG. 3, and thusidentified with same reference numerals as those used in FIG. 3.

[0056] In the structure in FIG. 4, the relation of the opening diameterat the interface between the first insulating film 14 and the secondinsulating film 15 is defined such that the opening diameter in thefirst insulating film<the opening diameter in the second insulating filmis obtained, and therefore the same effects as in the first embodimentare obtained.

[0057]FIG. 5 is a sectional view showing a part of a multilayer wiringstructure according to modified example 3 of the first embodiment.

[0058] A via hole (or wiring groove) 173 in FIG. 5 is different fromthat shown in FIG. 4 in that the via hole side surface of the firstinsulating film 14 is reverse-tapered. That is, the via hole sidesurface of the first insulating film 14 is reverse-tapered such that theopening diameter in the first insulating film 14 is smaller toward theinterface between the first insulating film 14 and the second insulatingfilm 15. Other parts or portions are the same as those used in FIG. 4,and thus identified with same reference numerals as those used in FIG.4.

[0059] In the structure in FIG. 5, the relation of the opening diameterat the interface between the first insulating film 14 and the secondinsulating film 15 is defined such that the opening diameter in thefirst insulating film<the opening diameter in the second insulating filmis obtained, and therefore the same effects as those in the firstembodiment are obtained. However, since in the present embodiment thevia hole side surface of the first insulating film 14 is reverselytapered, then the embedding characteristic of the metal wiring material(Cu, etc.) is degraded as compared with other examples.

[0060] As in modified example 2 shown in FIG. 4 of the first embodiment,when the opening edge of the first insulating film 14 is tapered by RIEor the like, the metal wiring material will be easily embedded.

[0061]FIG. 6 is a sectional view showing a part of a multilayer wiringstructure according to modified example 4 of the first embodiment.

[0062] A via hole (or wiring groove) 174 in FIG. 6 is different fromthat shown in FIG. 4 in that the via hole side surface of the firstinsulating film 14 is processed into a barrel shape (bowing shape) like,for example, a beer barrel, and the shoulder portion of the opening edgeof the first insulating film 14 is cut off, and others are the same asthose in FIG. 4, and thus identified with the same reference numerals asthose in FIG. 4.

[0063] In the structure in FIG. 6, the relation of the opening diameterat the interface between the first insulating film 14 and the secondinsulating film 15 is defined such that the opening diameter in thefirst insulating film<the opening diameter in the second insulating filmis obtained, and therefore the same effects as those in the firstembodiment are obtained. In this case, as in modified example 2 of thefirst embodiment shown in FIG. 4, when the opening edge of the firstinsulating film 14 is tapered by RIE or the like, embedding of the metalwiring material will be easier.

[0064] Other modified examples of the first embodiment will also berealized. In the first embodiment, for the simplicity of explanation,the sectional shape of the via hole is shown, however, the invention maybe also applied in the case of forming the structure of a via holecontacting a part of the bottom of the wiring grooves by dual damascene(DD) process.

SECOND EMBODIMENT

[0065]FIG. 7 is a sectional view showing a part of a multilayer wiringstructure, in which a wiring groove and a via hole are formed, of asemiconductor device according to a second embodiment of the presentinvention.

[0066] The structure shown in FIG. 7 is similar to the first embodiment,that is, a lower layer wiring 72 is buried in a first insulating film 71on a semiconductor substrate 70, and an interlayer insulating film 73 isformed on the lower layer wiring 72 and first insulating film 71. Theinterlayer insulating film 73 is comprised of a first insulating film 74formed on the lower layer wiring 72 and first insulating film 71 and asecond insulating film 75 laminated on the first insulating film 74.

[0067] In the dual damascene (DD) method, a wiring groove 76 and a viahole 77 are formed by using RIE process. The wiring groove 76 reaches ina depth the inside of the first insulating film 74 by way of theinsulating film 75, and the via hole 77 reaches the lower layer wiring72 from part of the bottom of the wiring groove 76 in the firstinsulating film 74. The damaged layer (not shown) formed, due to the RIEprocess, at the side surface of the first insulating film 74 fordefining the wiring groove 76 and via hole 77 is dissolved later in thewet etching process by using chemical solution containing HF, NHF₃ orthe like.

[0068] By performing this wet etching process for a predetermined periodof time or more, as in the first embodiment, the relation of the openingdiameter at the interface between the first insulating film 74 and thesecond insulating film 75 is defined such that the opening diameter inthe first insulating film<the opening diameter in the second insulatingfilm is obtained. Therefore, it is effective to prevent protrusion ofthe opening edge of the second insulating film 75 in the opening of thefirst insulating film 74. Thereafter, a barrier metal layer (not shown)is formed in the inside of the via hole 77 and wiring groove 76, andfurther a metal wiring material is buried, thereby forming via (notshown) and metal wiring (not shown).

[0069] In the structure shown in FIG. 7, since the relation of theopening diameter at the interface between the first insulating film 74and the second insulating film 75 is defined such that the openingdiameter in the first insulating film<the opening diameter in the secondinsulating film is obtained, the same effects as those in the firstembodiment are obtained.

[0070]FIG. 8 is a sectional view for explaining the condition of retreatamount B of the second insulating film in the repeated array shown inFIG. 7.

[0071] When two or more patterns of upper layer metal wiring arearranged, the retreat amount B of the second insulating layer 75 at theinterface between the insulating film 74 and the second insulating film75 should be properly defined at B<0.25 A, where A is a space betweenadjacent upper layer wirings (width of first insulating layer 74). Inother words, it is appropriate to set the difference to A/2 or less,which is between the width A of the first insulating film 74 and thewidth of the second insulating film 75 at the interface therebetween.

[0072] To distinguish the retreat by this setting of the secondinsulating film 75 from the retreat of the second insulating film 75 bythe process variation, the retreat amount B may be set to be equal to ormore than (B≧T) the film thickness T of a barrier metal film 78deposited inside of the groove when the metal wiring is formed. In otherwords, the difference between the width A of the first insulating layer74 and the width of the second insulating film 75 at the interfacetherebetween may be set to two times or more than the film thickness Tof the barrier metal film.

[0073] Similarly, in the foregoing first embodiment and its modifiedexamples, if the retreat amount B of the second insulating film 15 isset to be equal to or more than the film thickness T of the barriermetal 18 deposited when the via contact 19 is formed, then it ispossible to distinguish the retreat of the second insulating film 15 bythe setting from the retreat of the second insulating film 15 by theprocess variation.

MODIFIED EXAMPLE OF FIRST EMBODIMENT

[0074]FIG. 9 is a sectional view showing a part of a multilayer wiringstructure according to modified example 1 of the second embodiment.

[0075] In the second embodiment shown in FIG. 7, the wiring groove 76and via hole 77 are formed in the first insulating film 74. The firstinsulating film 74 may be formed in a multilayer structure, and itsexample is explained below.

[0076] The structure shown in FIG. 9 is different from that shown inFIG. 7 in that the first insulating film 74 has a three-layer structure,and the via hole 77 is formed in an insulating film 741 of the bottomlayer, and the wiring groove 76 is formed in an insulating film 742 ofthe intermediate layer and an insulating film 743 of the uppermostlayer. Other parts or portions are the same as those used in FIG. 7, andthus identified with same reference numerals as those used in FIG. 7.

[0077] In this case, a film of SiOC series is used in the insulatingfilm 743 of the uppermost layer in the first insulating film 74, and thesecond insulating layer 75 of a carbon concentration lower than that ofthe insulating film 743 is deposited on the insulating film 743. Therelation of the opening diameter at the interface between the SiOCseries insulating film 743 and the second insulating film 75 is definedsuch that the opening diameter in the series insulating film<the openingdiameter in the second insulating film. Meanwhile, since the insulatingfilm 742 of the intermediate layer and the insulating film 741 of thebottom layer of the first insulating film 74 are remote from the secondinsulating film 75, and hence the film quality is not particularlyspecified.

[0078] Also in the second embodiment, as the via hole in the modifiedexamples of the first embodiment, the sectional shape of the wiringgroove may be modified in various shapes.

[0079] In these embodiments, the Si oxide film containing carbon is usedas the first insulating films 14, 74, but it is also possible to useorganic films (for example, CF film, or CN(H) film) containing carbonand containing no Si.

[0080] According to the semiconductor device and the method ofmanufacturing the same according to the embodiments, protrusions are notformed in the opening of the wiring groove or via hole formed in theinterlayer insulating film, so that thin portions and disconnections arenot formed in the barrier metal film deposited when buried wiring isformed in the wiring groove or a via contact is formed in the via hole.Therefore, embedding of wiring material metal is enhanced, and alsoelectromigration and stress migration of buried wiring and via portionsmay be enhanced.

[0081] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; an interlayer insulating film formed on thesemiconductor substrate, the interlayer insulating film comprising afirst insulating film and a second insulating film formed on the firstinsulating film, the first insulating film comprising a silicon oxidefilm containing carbon of a concentration, the second insulating filmcomprising a silicon oxide film containing carbon of a concentrationlower than the concentration of the first insulating film or comprisinga silicon oxide film containing substantially no carbon, a via contactmade of a metal material embedded in a via hole formed in the interlayerinsulating film, a diameter of the via hole in the first insulating filmbeing smaller than that in the second insulating film at an interfacebetween the first insulating film and the second insulating film.
 2. Thesemiconductor device according to claim 1, in which a side surface ofthe second insulating film defines the via hole, and the side surface ofthe second insulating film is tapered.
 3. The semiconductor deviceaccording to claim 1, in which a side surface of the first insulatingfilm defines the via hole, and an edge portion of the side surface ofthe first insulating film, which is at an interface between the firstinsulating film and the second insulating film, is tapered.
 4. Thesemiconductor device according to claim 2, in which a side surface ofthe first insulating film defines the via hole, and an edge portion ofthe side surface of the first insulating film, which is at an interfacebetween the first insulating film and the second insulating film, istapered.
 5. The semiconductor device according to claim 1, in which asurface of the first insulating film defines the via hole, and thesurface of the first insulating film is reverse-tapered.
 6. Thesemiconductor device according to claim 2, in which a surface of thefirst insulating film defines the via hole, and the surface of the firstinsulating film is reverse-tapered.
 7. The semiconductor deviceaccording to claim 1, in which a surface of the first insulating filmdefines the via hole, and the surface of the first insulating film isbarrel-shaped.
 8. The semiconductor device according to claim 2, inwhich a surface of the first insulating film defines the via hole, andthe surface of the first insulating film is barrel-shaped.
 9. Thesemiconductor device according to claim 1, in which the via contact isprovided in the via hole formed in the interlayer insulating film, witha barrier metal provided between the via contact and the interlayerinsulating film, and a difference in width between the first insulatingfilm and the second insulating film at the interface between the firstinsulating film and the second insulating film is 2 T or more, where Tdenotes a film thickness of the barrier film.
 10. A semiconductor devicecomprising: a semiconductor substrate; an interlayer insulating filmformed on the semiconductor substrate, the interlayer insulating filmcomprising a first insulating film and a second insulating film formedon the first insulating film, the first insulating film comprising asilicon oxide film containing carbon of a concentration, the secondinsulating film comprising a silicon oxide film containing carbon of aconcentration lower than the concentration of the first insulating filmor comprising a silicon oxide film containing substantially no carbon, ametal wiring of a metal material embedded in a wiring groove formed inthe interlayer insulating film, a diameter of the wiring groove in thefirst insulating film being smaller than that in the second insulatingfilm at an interface between the first insulating film and the secondinsulating film.
 11. The semiconductor device according to claim 10, inwhich a side surface of the second insulating film defines the via hole,and the side surface of the second insulating film is tapered.
 12. Thesemiconductor device according to claim 10, in which a side surface ofthe first insulating film defines the via hole, and an edge portion ofthe side surface of the first insulating film, which is at an interfacebetween the first insulating film and the second insulating film, istapered.
 13. The semiconductor device according to claim 11, in which aside surface of the first insulating film defines the via hole, and anedge portion of the side surface of the first insulating film, which isat an interface between the first insulating film and the secondinsulating film, is tapered.
 14. The semiconductor device according toclaim 10, in which a surface of the first insulating film defines thevia hole, and the surface of the first insulating film isreverse-tapered.
 15. The semiconductor device according to claim 11, inwhich a surface of the first insulating film defines the via hole, andthe surface of the first insulating film is reverse-tapered.
 16. Thesemiconductor device according to claim 10, in which a surface of thefirst insulating film defines the via hole, and the surface of the firstinsulating film is barrel-shaped.
 17. The semiconductor device accordingto claim 11, in which a surface of the first insulating film defines thevia hole, and the surface of the first insulating film is barrel-shaped.18. The semiconductor device according to claim 10, in which two or moreof the metal wirings are provided in a side-by-side arrangement, and,when A denotes a width of the first insulating film, at the interfacebetween the first insulating film and the second insulating film, in adirection of the side-by-side arrangement of the metal wirings, adifference in width between the first insulating layer and the secondinsulating film, at the interface between the first insulating film andthe second insulating film, is A/2 or less.
 19. The semiconductor deviceaccording to claim 10, in which the metal wiring is provided in thewiring groove formed in the interlayer insulating film, with a barriermetal provided between the metal wiring and the interlayer insulatingfilm, and a difference in width between the first insulating film andthe second insulating film, at the interface between the firstinsulating film and the second insulating film, is 2 T or more, where Tdenotes a film thickness of the barrier film.
 20. A method ofmanufacturing a semiconductor device comprising: forming an interlayerinsulating film on a semiconductor substrate, the interlayer insulatingfilm comprising a first insulating film and a second insulating filmformed on the first insulating film, the first insulating filmcomprising a silicon oxide film containing carbon of a concentration,the second insulating film comprising a silicon oxide film containingcarbon of a concentration lower than the concentration of the firstinsulating film or comprising a silicon oxide film containingsubstantially no carbon, forming a via hole in the interlayer insulatingfilm, removing a damaged layer formed on a side surface of the firstinsulating film which defines a portion of the via hole, the damagedlayer being formed when the via hole is formed, and retreating a sidesurface of the second insulating film which defines a portion of the viahole, and embedding a metal material in the via hole to form a viacontact in the via hole.
 21. A method of manufacturing a semiconductordevice comprising: forming an interlayer insulating film on asemiconductor substrate, the interlayer insulating film comprising afirst insulating film and a second insulating film formed on the firstinsulating film, the first insulating film comprising a silicon oxidefilm containing carbon of a concentration, the second insulating filmcomprising a silicon oxide film containing carbon of a concentrationlower than the concentration of the first insulating film or comprisinga silicon oxide film containing substantially no carbon, forming awiring groove in the interlayer insulating film, removing a damagedlayer formed on a side surface of the first insulating film whichdefines a portion of the wiring groove, the damaged layer being formedwhen the wiring groove is formed, and retreating a side surface of thesecond insulating film which defines a portion of the wiring groove, andembedding a metal material in the via hole to form a metal wiring in thewiring groove.